000			01192cam a22002774i 4500
005			20260115032035.0
008			130415s2007 xxu dg 000 0 eng d
020			_a9781420051544
040			_aMPL _cMPL _erda
041	0		_aara
082	0	0	_a621.8 _221
100	1		_aCavanagh, Joseph
245	1	0	_aVerilog HDL _bDigital design and modeling _cJoseph Cavanagh
250			_a[1st ed.]
264		0	_aFlorida, USA _bCRC press _c2007
300			_a900 pages _billustrations _c30 سم
336			_aنص
337			_aبدون وسيط
338			_aكتاب
500			_aIncludes bibliographical references and index
520	2		_athis eddition provides descriptions of the design module, the test bench module, the outputs obtained from the simulator, and the waveforms obtained from the simulator illustrating the complete functional operation of the design. Where applicable, a detailed review of the topic's theory is presented together with logic design principles, including state diagrams, Karnaugh maps, equations, and the logic diagram
650	1	0	_aComputer industry
650	1	0	_aComputer programming
650	1	0	_aElectrical engineering
650	1	0	_aProgramming languages
999			_c77787 _d77787